IBM unveiled its new chip technology with a transistor size of 0.7 nanometers (7 angstroms), making it the world's first sub-1 nanometer chip as of June 25, 2026 [1, 2, 3]. The chip packs nearly 100 billion transistors onto a silicon chip no larger than a human fingernail [4, 1, 2, 5, 3].
This new architecture, named "NanoStack," stacks transistors vertically in three dimensions instead of the traditional flat layout. This design significantly increases transistor density [4, 1, 2, 3]. Jay Gambetta, director of IBM Research, said, "With our new NanoStack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency" [4].
Compared to IBM's prior 2nm chips introduced in 2021, the 0.7nm chip delivers up to 50% higher performance and 70% greater energy efficiency [4, 1, 2, 5, 3]. Gambetta described the technology as enabling "a future where computing becomes significantly more powerful without a corresponding increase in energy" [3].
Currently, industry-standard chips are around 2 nanometers, with Intel recently moving its 1.8nm process to a risk production phase last week on June 18 [1, 2]. IBM has previously licensed chip tech to Samsung and Japan's Rapidus but has not named a manufacturing partner for this new chip technology [1, 2].
IBM expects to start mass production of its NanoStack chips within about five years from 2026 [1, 2, 3]. The company’s advancement marks a significant step in transistor innovation and chip performance.
