IBM introduced its new NanoStack chip technology on June 25, featuring transistor architecture of 0.7 nanometers (7 angstroms), marking what the company says is the world’s first chip technology below 1 nanometer [1, 2, 3, 4].
The chip uses a three-dimensional stacking design called NanoStack, which vertically stacks three nanosheet transistors to pack nearly 100 billion transistors on a silicon chip roughly the size of a fingernail [1, 2, 3, 4]. This doubles the transistor density of IBM’s 2 nanometer chip launched in 2021 [1, 2, 3, 4].
IBM said the new chip delivers up to 50% higher performance and 70% greater energy efficiency compared to its 2nm predecessor [1, 2, 3, 4]. Jay Gambetta, director of IBM Research, said, "With our new NanoStack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency" [1, 2, 3].
The transistor design features nanosheets about 5 nanometers thick, separated by 9 nanometers, each consisting of 15 rows of silicon atoms [4].
IBM has licensed previous chip tech to Samsung and Japan’s Rapidus but has not announced a manufacturing partner for the 0.7nm NanoStack technology [2, 3, 4]. The company expects production readiness in about five years [2, 3, 4]. An industry source noted Rapidus aims to produce 2nm chips at scale starting in the second half of 2027, suggesting IBM’s production timeline may be optimistic [4].
Intel recently announced risk production of 1.8nm chips under its 18A process on June 18, about a week before IBM’s announcement [2, 3].
IBM’s achievement marks a new milestone in transistor miniaturization and chip performance, with nearly twice the transistor density and significant gains in speed and energy savings compared to the prior 2nm technology. The company plans to ready the NanoStack process for manufacturing by around 2031 [2, 3, 4].
